1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having a structure in which a plurality of semiconductor chips are bonded to a surface of a solid (for example, a semiconductor chip or a wiring board) and a method of assembling the same.
2. Description of Related Art
In order to increase a substantial integration degree of a semiconductor device, a semiconductor device having a chip-on-chip structure in which semiconductor chips in two layers are overlapped with each other has been paid attention to.
Specifically, a pad opening where internal wiring is partially exposed is provided on a device formation surface of each of semiconductor chips to be overlapped, for example. A projection electrode called a “bump” is provided in the pad opening. The semiconductor chips are overlapped with each other by so-called face-to-face bonding.
For example, one of the semiconductor chips is larger than the other semiconductor chip, and is taken as a mother chip or primary chip having an electrode for external connection. That is, an electrode is provided on a device formation surface of the primary chip, for example. The electrode is electrically connected to an electrode on an underlying substrate (a wiring board), and an external connecting electrode is provided on the underlying substrate. When the semiconductor device is mounted, the external connecting electrode on the underlying substrate is soldered to a printed board or a ceramic board.
There may, in some cases, be a plurality of semiconductor chips (daughter chip or secondary chips) to be overlapped with the primary chip. In this case, the secondary chips must be accurately aligned with and joined to the primary chip. The secondary chips are generally mounted on the primary chip one at a time. Accordingly, a mounting operation is repeatedly performed, and the number of times the operation is performed corresponds to the number of secondary chips. Therefore, a long time period is required for assembling. Since there are a plurality of secondary chips, the probability that the secondary chips are erroneously bonded or mounted (an erroneous mounting rate) is considerably high.